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Project 1 : Digital Upconverter

The Digital Upconverter is a single board pci based (PCI 104) module which allows a user to transmit IF waveforms.

There are a total of 2 unique FPGA and 1 CPLD designs in the system. The two FPGAs are the PCI/Boot (SpartanIIe-300) and the Upconverter (SpartanIII-1500). A CPLD accepts a serial interface from the Boot FPGA, and extracts data/address and presents in parallel to ATMEL flash. On power up, the PCI/Boot FPGA is loaded from a configuration serial E2. When this FPGA has booted, it then accesses the ATMEL flash for an initialization image for the Upconverter FPGA. The boot process is available for SBC monitoring thru PCI status registers.

The Upconverter FPGA initializes both the AD9854 and the AD9857. It then performs phase calibration, the alignment of the AD9857 output with the PPS leading edge. When clock alignment is complete, the 512 MB DRAM is initialized, and this final step of initialization results in an IRQ to the SBC.

There are three operational modes for transmission. The first utilizes the character data fifo which is loaded at the bit transmit rate over the pci. Each bit of a word is then used to select 1 of 2 biphase values. The second mode allows the user to load the 512 MB DRAM with a continuous stream of IQ values with IQ clk rate (25Mhz) resolution. The third mode is a hybrid, where bit values are loaded into the character data fifo, and a Gold Code is loaded into the DRAM, and the XOR is used to select a biphase IQ pair.

Project 2 : RF Modem : Demodulator Section

The RF Modem Demodulator is a PCI based (PC104) PWB with two channels of RF inputs, Ch1 is the platform tx output and Ch2 is the rx input from the other channel. The two channels allow this board to be used in two way time transfer for sub ns alignment of system clocks between two non-colocated platforms. 4 FPGAs and 5 TI320C6713B DSPs.

The system contains 4 unique FPGA designs. The four FPGAs are : Flash Interface/Boot FPGA (SpartanIIe-100), 2 Channel Downconverter FPGA (SpartanIIe-300), IQ Router FPGA(SpartanIIe-300), and the PCI Interface/Serial Crossbar Switch FPGA.

The Flash Interface/Boot FPGA is loaded on PWB powerup from a Xilinx serial E2PROM. This FPGA boot each of the three FPGAs by accessing one of 8 256Kbyte regions of flash to obtain the associated image for the three FPGAs. The other 5 256K regions of flash are reserved for each of five DSPs. The PCI Interface/ Serial Crossbar Switch FPGA contains a boot status register for the attached SBC to monitor boot status via the PCI. When this is complete, the SBC will then command the booting of DSP[5:1] thru the Boot FPGA. The DSPs on executing their boot code issue a boot message to the SBC thru the PCI/Serial Crossbar Switch FPGA.

The system operates by commanding the IQ router to start collecting packets of IQ data from 2 channel digitizer. The IQ router generates an IRQ to the receiving DSP, and inserts a four word header into the IQ packet block. A receiving DSP can issue slew commands to the IQ router to re-align IQ packet boundaries to the received/demodulated bit stream boundard.

The Serial Crossbar Switch allows non-blocking communication between any node on the switch port. All messages are buffered within the switch until the complete message is received. Messages that are sent between DSPs are retransmitted from the Serial Crossbar switch at a 1/4 rate from which they are received. [Message traffic bandwidth analysis indicated the reduced bandwith would not be a problem.] This was to solve a problem where IRQs generated within the receive MCASP port were dropped when spacing of IRQs was too short. Statistic counters present in the PCI/Serial Crossbar Switch FPGA were present for quality-of-service debugging.

Project 3 : JPL Deep Space Network Timing Distribution System

The Deep Space Network Timing Distribution System is comprised of a central Timing Control Generator which maintains station time via a VCXO based PLL which is locked to external 100Mhz station clock. Once per second, the TCG outputs a synchronized time code (STC) over Fiber Optic Transmit ports. The STC is transmitted through multiple levels of Distribution Assemblies, each providing a 1 to 10x optical redrive function. The network endpoints are TCTs, Time Code Translaters. The TCT decodes the STC once per second, and updates its own station time reference, and provides accurate time translation to the following standards : IRIG-B (Analog and DC-level), NASA-36 (Analog and DC-level), RS-232, PBCD, PB-1, and Pulse Rate Outputs.

There are a total of 4 unique FPGA designs and 2 CPLD designs in the system. The four FPGAs are : TCG (SpartanIIe-300), DA-Input(SpartanIIe-50), TCT(SpartanIIe-300), Flywheel(SpartanIIe-50). A microcontroller within the front panel passes commands via a serial interface to the TCG FPGA for initializing station time, slewing time (+/-), setting/clearing leap second events. The TCG FPGA maintains station time BCD counters, as well as the reference PPS counter. Once per second it formats the STC for transmission. The DA Input FPGA performs a receive CRC check on the incoming STC, and generates a local encoded optical PPS when a CRC check is good. The TCT performs all remote station time maintenance, and translation to all external interface time standards. The Flywheel FPGA monitors the PLL VCXO, and when a loss-of-lock condition is detected, redrives the VCXO control voltage with a stable voltage thru a DA to maintain mimimal drift.

Project 4 : ALMDS System Architecture Definition and FPGA Design

ALMDS is an Airborn LADAR imaging system utilizing four high speed (300 Hz 512x128 pixels) Dalsa Video Cameras. A Virtex near each Dalsa collected digital video data, and buffered in separate DDR using a staggered memory address scheme to implement rotation. Buffered frames were forwarded over LVDS interface to a Virtex II on a remote PWB. This Data Link FPGA merged data from the four cameras, and either sent the frame to a Sharc based DSP array over LVDS interface, or sent frame over a Fiber Optic link ( Agilent HDMP-1022/1024 SerDes) to high BW data recorder. A playback function on optical receive path steered recorded data to DSP array.

There were four FPGA designs associated with this project : the camera interface FPGA, the Data Link FPGA, and the CEC interface FPGA were implemented with Virtex II devices, and the Fiber Optic Link FPGA was implemented in a Spartan II device.

Project 5 : Spartan II and Virtex Design Pair

Xilinx Spartan II design : Incorporated Xilinx PCI core, and developed peripheral interfaces to support W/R access to ATMEL FLASH device, as well as mapping PCI accesses to a local I/O port interface.  Support for performing a boot load of connected Virtex FPGA from flash contents was also designed.  Simulation model for the AT49BV008 1Mx8 flash generated to support board level simulation. 

Xilinx Virtex Design : Virtex performs initialization of static parameters within an AD9854 DDS and AD9856 Upconverter.  Following stable DDS clock generation, the clock output is used for internal Virtex data transfer functions from a local I/O port interface connected to the PCI to the AD9856 digital upconverter.  Data from the PCI is buffered in synchronous DPM within the virtex, and flow control back to the host PCI initiator is achieved via interrupt control.   Simulation models for AD9854 and AD9856 generated to support board level simulation. 

 Project 6 : Spartan II and Virtex Design Pair

Xilinx Spartan II design : Spartan performs static initialization of XaQti11800FP Gigabit Ethernet controller.  Following initialization, Spartan II accepts ethernet frames in UDP format, and performs MAC level frame checking.  For matches, frame data extracted, and loaded into local holding registers, and interrupt asserted to host C60 DSP.  Upon I/O decode of command from C60, values transferred from local holding registers to attached Virtex device over block DMA like interface.  Simulation model for XaQti11800FP generated to support board level simulation.

Virtex Design : Two channel processing - each channel merges fixed length blocks of A/D data with header information processed by C60, and formats merged data into a UDP frame for ethernet transmission by XaQti11800 chip.  Data collected from A/D interface is variable rate, with max data rate of 100M samples/second.

Project 7 : Virtex design

On powerup - Virtex performs static initialization of XaQti11800FP for Rx mode operation.  Concurrently an external DDS, an AD9854 is initialized with various control parameters over a I/O interface.  Incoming ethernet frames are decomposed into control information for DDS tuning, and A/D data which is stored in external SDRAM.  A DRAM arbiter was created to interleave 32 word burst WRITEs with 32 word burst READS, as well as refresh cycles to the DRAM.  The READ data from the SDRAM is used to drive an external D/A to recreate the original analog waveform.  Simulation models for the AD9854 was created to emulate complex synchronization requirements during initialization.

Project 8 :  Embedded Core Processor (V8)Virtex Synthesis/cache controller design/ and hw/sw coverification.

A 3rd party microcontroller core designed for 25Mhz operation was retargeted for 50 Mhz operation.  Original extensive efforts yielded only 42Mhz operation, but use of floor planning of 96 block RAMs, and MPPR (iterative placements) in PAR yielded approximately 20% improvement in timing.  An 8 line cache offered 2 cycle access on cache miss, and 1 cycle access on cache hit.  Perl script was written to convert Intel Hex formatted file ( C compiler output of SW build ) to a vhdl constant file used for initialization of block RAMs during simulations.  This allowed for a HW/SW coverification environment.

Project 9 :  Fibre Channel Receive Port for FC emulator.

The Fibre Channel (FC) emulator was an i960 processor based pci card, with the i960 having interfaces to independant Tx and Rx 1Gbit FC ports.   The card was designed to plug into a pci slot of a Windows NT platform where a host application allowed the card to act as either a FC data collector, or as a more sophisticated FC emulation port.  FC-AL support was present in both the FC Tx and Rx channels.   The Tx and Rx channel control was implemented in Xilinx 4000 series FPGAs, and provided real time FC link layer control, data collection of FC primitives and time stamping of primitive transitions, FC frame capture, and a real time interrupt driven interface to the i960.

 

 

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Last modified: June 10, 2006